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MicreL, Inc.
Precision Edge 3.3V 1GHz DUAL 1:10 PRECISION SY89828L Precision Edge(R) LVDS FANOUT BUFFER/ SY89828L TRANSLATOR WITH 2:1 INPUT MUX
(R)
FEATURES
High-performance dual 1:10, 1GHz LVDS fanout buffer/translator Two banks of 10 differential LVDS outputs Guaranteed AC parameters over temperature and voltage: * > 1GHz fMAX * < 50ps within device skew * < 400ps tr, tf time Each bank includes a 2:1 input mux 2:1 mux input accepts LVDS and LVPECL Low jitter performance * < 1psRMS cycle-to-cycle jitter * < 1psPP total jitter 3.3V supply voltage Output enable function LVDS input includes internal 100 termination Available in a 64-Pin EPAD-TQFP Precision Edge(R)
DESCRIPTION
The SY89828L is a precision fanout buffer with 20 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination. The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL1 and CLK_SEL2 pins. The Output Enables (OE1 and OE2) are synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89828L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs. The SY89828L is available in a single space saving package, enabling a lower overall cost solution.
APPLICATIONS
Enterprise networking High-end servers Communications
TYPICAL APPLICATION CIRCUIT
100
Primary Card
Primary Clock Source LVDS_CLKA /LVDS_CLKA
5 5
Backup Clock Source LVDS_CLKB /LVDS_CLKB
5 5
100
Redundant Card
SEL1 Primary/Backup Clock Select (Switchover with 2.0ns)
System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application. LVPECL inputs not shown in this application. Precision Edge is a registered trademark of Micrel, Inc. M9999-012208 hbwhelp@micrel.com or (408) 955-1690
Rev.: D Amendment: /0
1
Issue Date: January 2008
Micrel, Inc.
Precision Edge(R) SY89828L
PACKAGE/ORDERING INFORMATION
VCCO Q0 /Q0 Q1 /Q1 Q2 /Q2 Q3 /Q3 Q4 /Q4 Q5 /Q5 Q6 /Q6 VCCO
Ordering Information(1)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GNDO Q7 /Q7 Q8 /Q8 Q9 /Q9 VCCO VCCO Q10 /Q10 Q11 /Q11 Q12 /Q12 GNDO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEL2 LVDS_CLKB /LVDS_CLKB VCCI LVDS_CLKA /LVDS_CLKA CLK_SEL1 LVPECL_CLKA /LVPECL_CLKA GNDI OE1 LVPECL_CLKB /LVPECL_CLKB CLK_SEL2 OE2 SEL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCO /Q19 Q19 /Q18 Q18 /Q17 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 /Q13 Q13 VCCO
Part Number SY89828LHI(2) SY89828LHITR(2) SY89828LHY(2) SY89828LHYTR(2)
Package Type H64-1 H64-1 H64-1 H64-1
Operating Range Industrial Industrial Industrial Industrial
Package Marking SY89828LHI SY89828LHI
Lead Finish Sn-Pb Sn-Pb
SY89828LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89828LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Pb-Free package recommended for new designs.
64-Pin TQFP (H64-1)
FUNCTIONAL BLOCK DIAGRAM
100 termination internal CLK_SEL1 LVDS_CLKA /LVDS_CLKA SEL1 OE1
0 0
10 10
LVPECL_CLKA /LVPECL_CLKA
Q0 - Q9 /Q0 - /Q9
1 1
100 termination internal
LEN
Q
D LVDS_CLKB /LVDS_CLKB
0
0
10 10
Q10 - Q19 /Q10 - /Q19
1
LVPECL_CLKB /LVPECL_CLKB D CLK_SEL2 SEL2 OE2
1
LEN
Q
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MicreL, Inc.
Precision Edge(R) SY89828L
PIN DESCRIPTIONS
Pin Number 5, 6 Pin Name LVDS_CLKA /LVDS_CLKA I/O Input Type LVDS Internal P/U 3.5k Pull-up See Fig. 2 3.5k Pull-up See Fig. 2 75k pull-down See Fig. 1 75k pull-down See Fig. 1 11k Pull-up 11k Pull-up 11k Pull-up 11k Pull-up 11k Pull-up 11k Pull-up Pin Function Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. Has internal 100 termination. Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. Has internal 100 termination. Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating. Floating input, if selected produces a LOW at output. Requires external termination. Differential clock input selected by CLK_SEL2, SEL1 and SEL2. Requires external termination. Selects LVDS_CLKA input when LOW and LVPECL_CLKA input when HIGH. Selects LVDS_CLKB input when LOW and LVPECL_CLKB input when HIGH. Selects input source CLKA when LOW and CLKB when HIGH for outputs Q0 - Q9 and /Q0 - /Q9. Selects input source CLKA when LOW and CLKB when HIGH for outputs Q10 - Q19 and /Q10 - /Q19. Enable input synchronized internally to prevent output glitches or runt pulses. Enable input synchronized internally to prevent output glitches or runt pulses. Core VCC connected to 3.3V supply. Not connected to VCCO internally. Connected to VCCO on PCB. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCC pins as possible. Output buffer VCC connected to 3.3V suppy. Not connected to VCCI internally. Connected to VCCI on PCB. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCC pins as possible. Core ground not connected to GNDO internally. To be connected to GNDO on PCB. Output buffer ground not connected to GNDI internally. To be connected to GNDI on PCB. LVDS Differential clock outputs from CLKA when SEL1 = LOW and from CLKB when SEL1 = HIGH. Q outputs are static when OE1 = LOW. Unused output pair must be terminated with 100 to maintain low jitter and skew. Differential clock outputs (complement) from CLKA when SEL1 = LOW and from CLKB when SEL1 = HIGH. /Q outputs are static HIGH when OE1 = LOW. Unused output pairs must be externally terminated with 100 to maintain low jitter and skew. Differential outputs from CLKA when SEL2 = LOW and from CLKB when SEL2 = HIGH. Q outputs are static LOW when OE2 = LOW. Unused output pairs must be externally terminated with 100 to maintain low jitter and skew.
2, 3
LVDS_CLKB /LVDS_CLKB
Input
LVDS
8, 9
LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB CLK_SEL1 CLK_SEL2 SEL1 SEL2 OE1 OE2 VCCI
Input
LVPECL
12, 13
Input
LVPECL
7 14 16 1 11 15 4
Input Input Input Input Input Input Power
LVTTL/ CMOS LVTTL/ CMOS LVTTL/ CMOS LVTTL/ CMOS LVTTL/ CMOS LVTTL/ CMOS
17, 32, 40, 41, 49, 64
VCCO
Power
10 33, 48 63, 61, 59, 57, 55 53, 51, 47, 45, 43
GNDI GNDO Q0 - Q9
Power Power Output
62, 60, 58, 56, 54 52, 50, 46, 44, 42
/Q0 - /Q9
Output
LVDS
39, 37, 35, 31, 29 27, 25, 23, 21, 19
Q10 - Q19
Output
LVDS
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Micrel, Inc.
Precision Edge(R) SY89828L
Pin Number 38, 36, 34, 30, 28 26, 24, 22, 20, 18
Pin Name /Q10 - /Q19
I/O Output
Type LVDS
Internal P/U
Pin Function Differential outputs (complement) from CLKA when SEL2 = LOW and from CLKB when SEL2 = HIGH. /Q outputs are static HIGH when OE2 = LOW. Unused output pairs must be externally terminated with 100 to maintain low jitter and skew.
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MicreL, Inc.
Precision Edge(R) SY89828L
TRUTH TABLE
OE1(1) OE2(1) SEL1(1) SEL2(1) CLK_SEL1(1) CLK_SEL2(1) 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 X X X X 0 0 1 1 X 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 X X X X X 0 1 0 0 1 1 0 0 1 1 X X 0 1 X X 0 1 X X X X X 0 1 0 1 0 1 0 1 0 1 X X 0 1 X X 0 1 X Q0 - Q9 /Q0 - /Q9 Q10 - Q19 /Q10 - /Q19
LVDS_CLKA /LVDS_CLKA LVDS_CLKA /LVDS_CLKA LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA LVDS_CLKA /LVDS_CLKA LVDS_CLKB /LVDS_CLKB LVDS_CLKA /LVDS_CLKA LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB LVDS_CLKB /LVDS_CLKB LVDS_CLKA /LVDS_CLKA LVPECL_CLKB /LVPECL_CLKB LVDS_CLKA /LVDS_CLKA LVDS_CLKB /LVDS_CLKB LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB LVDS_CLKB /LVDS_CLKB LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB LOW LOW LOW LOW HIGH HIGH HIGH HIGH LVDS_CLKA /LVDS_CLKA LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB LVPECL_CLKB /LVPECL_CLKB LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH
LVDS_CLKA /LVDS_CLKA LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB LVPECL_CLKB /LVPECL_CLKB LOW HIGH
NOTE: 1. Input has internal pull-up so floating input = 1.
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Micrel, Inc.
Precision Edge(R) SY89828L
Absolute Maximum Ratings(Note 1)
Power Supply Voltage (VCCI, VCCO) .............. -0.5 to +4.0V Input Voltage (VIN) ........................................... -0.5 to VCCI Output Current (IOUT) ............................................... 10mA Storage Temperature (TS) ........................... -65 to +150C ESD Rating, Note 3 ...................................................... 1kV
Operating Ratings(Note 2)
Supply Voltage ............................................... +3V to +3.6V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance TQFP (JA) Exposed pad soldered to GND Still-Air (multi-layer PCB) ................................. 23C/W -200lfpm (multi-layer PCB) ............................. 18C/W -500lfpm (multi-layer PCB) ............................. 15C/W Exposed pad NOT soldered to GND (not recommened) Still-Air (multi-layer PCB) ................................. 44C/W -200lfpm (multi-layer PCB) ............................. 36C/W -500lfpm (multi-layer PCB) ............................. 30C/W TQFP (JC) ......................................................... 4.4C/W
DC ELECTRICAL CHARACTERISTICS
Power Supply: TA = -40C to +85C
Symbol VCCI, VCCO ICCI ICCO Parameter VCC Core, VCC Output ICC Core ICC Output Condition Note 4 Max. VCC No Load, Max. VCC Min 3.0 Typ 3.3 45 160 Max 3.6 70 260 Units V mA mA
LVDS Input: VCC = 3.3V 10%, TA = -40C to +85C
Symbol VIN VID IIL RIN
Note 1.
Parameter Input Voltage Range Differential Input Swing Input LOW Current LVDS Differential Input Resistance (LVDS_CLK to /LVDS_CLK)
Condition
Min 0 100 -1.25 80
Typ
Max 2.4
Units V mV mA
100
120
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Devices are ESD sensitive. Handling precautions recommended. VCCI and VCCO must be connected together on the PCB such that they remain at the same potential. VCCI and VCCO are not internally connected on the die.
Note 2. Note 3. Note 4.
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MicreL, Inc.
Precision Edge(R) SY89828L
DC ELECTRICAL CHARACTERISTICS
LVPECL Input: VCC = 3.3V 10%, TA = -40C to +85C
Symbol VIH VIL VPP VCMR IIH IIL
Note 5. Note 6.
Parameter Input HIGH Voltage (Single-Ended) Input LOW Voltage Minimum Input Swing (LVPECL_CLK)
Condition
Min VCC -1.165 VCC -1.945
Typ
Max VCC -0.880 VCC -1.625 VCCI -0.4 150
Units V V mV V A A
Note 5
300 GNDI +1.8
Common Mode Range (LVPECL_CLK) Note 6 Input HIGH Current Input LOW Current
0.5
The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). CMR range varies 1:1 with VCCI. VCMR (min) is fixed at GNDI + 1.8V.
CMOS/LVTTL: VCC = 3.3V 10%, TA = -40C to +85C
Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current VIN = VCC VIN = 0.5V -600 Condition Min 2.0 0.8 150 Typ Max Units V V A A
LVDS Output: VCC = 3.3V 10%, TA = -40C to +85C
Symbol VOD VOH VOL VOCM VOCM
Note 7. Note 8.
Parameter Differential Output Voltage Output HIGH Voltage Output LOW Voltage Output Common Mode Voltage Change in Commom Mode Voltage
Condition Note 7, 8 Note 7 Note 7 Note 8
Min 250
Typ 350
Max 400 1.474
Units mV V V
0.925 1.125 -50 1.375 50
V mV
Measured as per Figure 3, 100 across Q and /Q outputs. Measured as per Figure 4.
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Micrel, Inc.
Precision Edge(R) SY89828L
AC ELECTRICAL CHARACTERISTICS(NOTE 1)
VCC = 3.3V 10%, TA = -40C to +85C, unless noted. Symbol fMAX tPHL tPLH Parameter Maximum Toggle Frequency Differential Propagation Delay Note 3 Condition Note 2 LVPECL Input: 150mV LVPECL Input: 800mV LVDS Input: 100mV LVDS Input: 400mV tSWITCHOVER tS(OE) tH(OE) tSKEW Clock Input Switchover Output Enable Set-Up Time Output Enable Hold Time Within Device Skew Part-to-Part Skew tJITTER tr, tf
Note 1. Note 2. Note 3. Note 4.
Min 1.0 0.950 0.80 1.10 0.950
Typ
Max
Units GHz
1.15 1.0 1.35 1.20 1.55
1.45 1.3 1.60 1.450 1.85
ns ns ns ns ns ns ns
CLK_SEL to Valid Output Note 4 Note 4 Note 5 Note 6 Note 7 Note 8 200 0C to +85C -40C 1.0 0.5
25 35
50 75 400
ps ps ps psRMS psPP ps
Cycle-to-Cycle Total Jitter Output Rise/Fall Times (20% to 80%)
<1 290
<1 2 400
100 termination between Q and /Q outputs. Airflow 300lfpm, or exposed pad soldered to ground plane. fMAX is defined as the maximum toggle frequency, measured with a 750mV LVPECL input or 350mV LVDS input. Outut swing is > 200mV. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device identical input transition, operating at the same voltage and temperature. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC = Tn -Tn+1 where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peakto-peak jitter value.
Note 5. Note 6. Note 7. Note 8.
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MicreL, Inc.
Precision Edge(R) SY89828L
TYPICAL OPERATING CHARACTERISTICS
(Conditions: VCC = 3.3V, TA = 25C, unless otherwise stated)
400 350 300 250 200 150 100 50 0
PROPAGATION DELAY (ps)
OUTPUT VOLTAGE (mV)
500 450
Output Amplitude vs. Frequency
Nominal Propagation Delay vs. Temperature 2000 LVPECL IN = 750mV 1800 LVDS IN = 250mV 1600 LVDS INPUT 1400 1200 1000 800 600 400 200 0 -50
LVPECL INPUT
0
200 400 600 800 1000 1200 FREQUENCY (MHz)
-25 0 25 50 75 TEMPERATURE (C)
100
2000 1800 1600 1400 1200 1000 800 600 400 200 0
Propagation Delay vs. Input Amplitude SWITCHOVER TIME (ns) LVDS INPUT
1800 1600 1400 1200 1000 800 600 400 200 0 -50
CLK_SEL Switchover Time vs. Temperature
PROPAGATION DELAY (ns)
LVPECL INPUT
0
200 400 600 800 1000 INPUT AMPLITUDE (mV)
-25 0 25 50 75 TEMPERATURE (C)
100
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Micrel, Inc.
Precision Edge(R) SY89828L
FUNCTIONAL CHARACTERISTICS
155MHz Output
TA = 25C VCC = 3.3V TA = 25C VCC = 3.3V
622MHz Output
Output Swing (50mV/div.)
TIME (500ps/div.)
Output Swing (50mV/div.)
TIME (200ps/div.)
1GHz Output
TA = 25C VCC = 3.3V
Output Swing (50mV/div.)
TIME (100ps/div.)
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MicreL, Inc.
Precision Edge(R) SY89828L
LVPECL/LVDS INPUTS
VCC
VCC
1.9k 1.9k
LVPECL_CLK 75k 75k
LVDS_CLK
1.4k
1.4k
100
/LVPECL_CLK GND
/LVDS_CLK
GND
Figure 1. Simplified LVPECL Input Stage
Figure 2. Simplified LVDS Input Stage
LVDS OUTPUTS
LVDS stands for Low Voltage Differential Swing. LVDS specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is also kept tight, to keep EMI low.
vOD vOH, vOL vOH, vOL
100
50, 1%
50, 1%
vOCM, vOCM
GND
Figure 3. LVDS Differential Measurement
GND
Figure 4. LVDS Common Mode Measurement
QOUT 350mV (typical) /QOUT
Figure 5. Output Driver Signal Levels (Single-Ended)
QOUT 750mV QOUT - /QOUT /QOUT
Figure 6. Output Driver Signal Levels (Differential)
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Micrel, Inc.
Precision Edge(R) SY89828L
DETAILED DESCRIPTION
The SY89828L is a precision dual 1:10 fanout buffer. It allows either LVPECL or LVDS inputs, selectable by an input muxes, and outputs 2 sets of 10 LVDS output pairs. The device features 2 synchronous output enables. The SY89828L provides extremely low skew across its outputs. LVPECL_CLKA, LVPECL_CLKB The SY89828L allows two inputs with standard LVPECL voltage swings. These inputs may be adjusted per the data sheet characteristics regarding the CMR and minimum input swing. As the SY89828L contains no appropriate internal termination, upstream devices need to be properly terminated to provide the proper LVPECL input swing. If not being used (CLK_SEL1 and CLK_SEL2 are LOW), these input pairs may be left floating, as they are internally terminated to ground via 75k pull-down resistors. LVDS_CLKA, LVDS_CLKB The SY89828L allows two inputs with standard LVDS voltage swings. The SY89828L provides an appropriate internal 100 termination resistor. Hence, upstream LVDS devices do not require external termination to drive the SY89828L. If not being used (CLK_SEL1 and CLK_SEL2 are HIGH), these inputs pair may be left floating. SEL1, SEL2 TTL Inputs The SEL1 Input is used to select either CLKA (SEL1 is LOW) or CLKB (SEL1 is HIGH) for the Q0-Q9 differential output pairs. In a similar manner, The SEL2 Input is used to select either CLKA (SEL2 is LOW)or CLKB (SEL2 is HIGH) for the Q10-Q19 differential output pairs. CLK_SEL1, CLK_SEL2 TTL Inputs The CLK_SEL1 Input is used to select either LVDS_CLKA (CLK_SEL1 is LOW) or LVPECL_CLKA (CLK_SEL1 is HIGH). In a similar manner, The CLK_SEL2 Input is used to select either LVDS_CLKB (CLK_SEL2 is LOW) or LVPECL_CLKB (CLK_SEL2 is HIGH). OE1, OE2 TTL Inputs The SY89828L's output enable functions are designed to disable the outputs only when the outputs are LOW. The OE1 TTL Input controls the Q0-Q9 outputs and OE2 controls the Q10-Q19 outputs. This avoids the possibility of generating runt pulses. The OE1 and OE2 inputs are asynchronous inputs, but operate as synchronous enables. For synchronous operation, please adhere to the specific setup and hold times. When disabled, the Q outputs are LOW and the /Q outputs are HIGH. Q0-Q9, Q10-Q19 LVDS Outputs The SY89828L's LVDS outputs swing typically 350mV around a 1.25V common mode voltage above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input is kept tight to keep EMI low. Each of the SY89828L's LVDS outputs should be terminated with a 100 termination resistor including any unused output pairs. This ensures the best jitter and skew performance of the device. In a similar manner, The SEL2 Input is used to select either CLKA (SEL2 is LOW)or CLKB (SEL2 is HIGH) for the Q10Q19 differential output pairs.
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number SY55855V SY89825U SY89826U SY89829U M-0317 Exposed pad Function Dual CML/PECL/LVPECL-to-LVDS Translator 2.5/3.3V 1:22 High-Performance, Low-Voltage PECL Bus Clock Driver & Translator w/Internal Termination 3.3V 1GHz Precision 1:22 LVDS Fanout Buffer with 2:1 Input Mux 2.5/3.3V High-Performance, Dual 1:10 LVPECL Clock Driver w/Internal Termination & Redundant Switchover HBW Solutions Amkor Exposed Pad Application Note Data Sheet Link www.micrel.com/product-info/products/sy55855v.shtml www.micrel.com/product-info/products/sy89825u.shtml www.micrel.com/product-info/products/sy89826u.shtml www.micrel.com/product-info/products/sy89829u.shtml www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/ePad.pdf
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MicreL, Inc.
Precision Edge(R) SY89828L
64-PIN EPAD-TQFP (DIE UP) (H64-1)
+0.05 -0.05 +0.002 -0.002
+0.05 -0.05 +0.012 -0.012
+0.03 -0.03 +0.012 -0.012
+0.15 -0.15 +0.006 -0.006
+0.05 -0.05 +0.002 -0.002
Rev. 02
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package Package Notes: Note 1. Package meets Level 3 qualifications. Note 2. All parts are 100% baked and dry-packed before shipment. Note 3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC.
TEL
2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
FAX
+ 1 (408) 944-0800
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2002 Micrel, Incorporated. M9999-012208 hbwhelp@micrel.com or (408) 955-1690
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